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| General-Purpose Power Controller (GPPC) PSB 2121 CMOS IC Features q Switched mode DC/DC-converter q CCITT ISDN compatible q Low power dissipation q Supply voltage range 8 to 70 V q Programmable input undervoltage protection q Programmable overcurrent protection q Soft start q Power housekeeping input q Oscillator synchronization input/output q High voltage CMOS-technology 70 V P-DSO-20-1 P-DIP-16 Type PSB 2121-P PSB 2121-T Version V A4/A5 V A4/A5 Ordering Code Q67100-H8646 Q67100-H6032 Package P-DIP-16 P-DSO-20-1 (SMD) The PSB 2121 is a pulse width modulator circuit designed for fixed-frequency switching regulators with very low power consumption. In telephony and ISDN systems a high conversion yield is crucial to maintain functionality in all supply conditions via "S" or "U" interfaces. The PSB 2121 design and technology realize high conversion efficiency and low power dissipation. It should be recognized that the PSB 2121 can also be used in numerous DC/DC-conversion systems other than ISDN-power supplies. Semiconductor Group 1 12.92 PSB 2121 The PSB 2121 Contains the Following Functional Blocks q Undervoltage lockout q Temperature compensated voltage reference q Sawtooth oscillator q Error amplifier q Pulse width modulator q Digital current limiting q Soft start q Double pulse inhibit q Power driver Together with few external components it provides a stable 5 V DC-supply for subscriber terminals (TEs) or network terminations (NTs). It can also be programmed for higher output voltages, e.g. to supply S-lines with 40 V. Pin Configurations (top view) P-DSO-20 P-DIP-16 Semiconductor Group 2 PSB 2121 Pin Definitions and Functions Pin No. Pin No. Symbol Input (I) P-DSO P-DIP Output (O) 1 2 4 5 6 1 2 3 4 5 Definition Reference voltage Positive current sense Negative current sense Ground Gate Function Output of the 4.0 V reference voltage. When the voltage difference between these two pins exceeds 100 mV, the digital current limiting becomes active. All analog and digital signals are referred to this pin. Totem-pole output driver, has to be connected with the gate of an external power switch. Output of the internal CMOS supply. Via VEXT the internal CMOScircuits can be supplied from an external DC-supply in order to reduce chip power dissipation. The capacitor at this pin determines the soft start characteristic. VREF IP IN GND GA O I I I O 7 6 VEXT I/O External supply 9 10 11 12 14 15 16 17 7 8 9 10 11 12 13 14 CSS VS PWMP EO I I I O I I I I/O Soft start capacitor Battery voltage Pulse width modulator Positive voltage sense Negative voltage sense Undervoltage detection VS is the positive input voltage. Non-inverting input of the pulse width modulator. Error amplifier output. Non-inverting input of the error amplifier. Inverting input of the error amplifier. The undervoltage lockout can be programmed via UV. VP VN UV SYNC Synchronization This pin can be used as an input for synchronization of the oscillator to an external frequency, or as an output to synchronize multiple devices. R-oscillator C-oscillator The external timing components of the ramp generator are attached to OR and OC. 19 20 15 16 OR OC I I Semiconductor Group 3 PSB 2121 Figure 1 GPPC Functional Diagram Semiconductor Group 4 PSB 2121 Absolute Maximum Ratings Parameter Supply voltage (pin VS) referred to GND Analog input voltage (pins IP, IN, PWMP, VP, VN, SYNC, OR, OC) referred to GND Reference output current (pin VREF) SYNC output current (pin SYNC) Error amplifier output current (pin EO) Z-current (pin VEXT) Output current (pin VEXT) Driver output current (pin GA) Ambient temperature under bias Storage temperature Symbol Limit Values 80 6 Unit V V VS VI A IO REF IO SYNC IO Amp IZ EXT IO EXT ID R TA Tstg -5 -5 -5 2 -5 -5 - 25 to 85 - 40 to 125 mA mA mA mA mA mA C C DC-Characteristics TA = 0 to 70 C, VS = 9 to 70 V Limit Values Parameter Supply current Reference VREF Output voltage Symbol min. typ. 30 max. 50 Unit A Test Condition IS VS EXT 6.2 V VREF O 3.92 4.0 4.08 V TA = 25 C IL = 0 mA, VS = 40 V VS = 20 to 60 V TA = 25 C IL = 0 mA IL = 0.1 to 0.3 mA VS = 40 V, TA = 25 C 0 ... 70 C Line regulation VREF Line 60 mV Load regulation VREF Load 20 40 mV Temperature stability Load current VREF TS IREF Load 25 0.5 mV mA Semiconductor Group 5 PSB 2121 DC-Characteristics (cont'd) Limit Values Parameter Symbol min. typ. max. Unit Test Condition Oscillator / SYNC / OC fOSC = 20 kHz, RT = 39 k 1%, RD = 0 , CT = 1 nF 1% Initial accuracy TA = 25 C Voltage stability Temperature stability Max. frequency Sawtooth peak voltage Sawtooth valley voltage H-sync output level L-sync output level Error Amplifier / EO / VP / VN Input offset voltage Input current Common mode range DC open loop gain Common mode rejection Unity gain bandwidth Supply voltage rejection H-output voltage L-output voltage 10 1 5 3 % % % kHz V V 5.25 0.8 V V fmax VS VS VSYNC H VSYNC L 200 3.0 1.6 2.4 250 3.2 1.8 3.5 0.2 RT = 27 k CT = 39 pF IL = - 0.5 mA VEXT = 6.3 V IL = 20 A VIO II CMR 1.8 60 60 0.5 60 4 3 10 25 4.5 mV nA V dB dB MHz dB GVO kCMR f kSVR VOH VOL 70 70 1 70 5.5 0.02 1 CL (pin) 10 pF IL = - 100 A IL = 10 A V V Current Limit Comparator IP / IN, TA = 25 C Sense voltage Input bias current Input voltage range Response time (signal at GA) VSense II VI tRes 85 0 100 0 1 115 100 1 2 mV nA V s VS = 40 V IN = 0 V IP = 0 200 mV Semiconductor Group 6 PSB 2121 DC-Characteristics (cont'd) Limit Values Parameter Pulse Width Modulator Duty cycle Under Voltage Detection UV Start up threshold Threshold hysteresis Soft Start CSS Charging current Output Driver GA Symbol min. typ. max. Unit Test Condition td 0 50 % V Hy 7 8 0.3 9 V V pin UV = VS pin UV = VS CT 2 4 8 A TA = 25 C H-output voltage L-output voltage Rise time Fall time Output current External Supply VEXT Output voltage Output current Input voltage Z-current Power consumption VOH VOL tr tf IO 4.5 0.3 130 70 VEXT 0.4 200 200 5 V V ns ns mA ISource = 5 mA ISink = 5 mA CL = 220 pF; VEXT = 6.3 V CL = 220 pF; VEXT = 6.3 V VO IO VI IZ Ptot 6.0 5.8 2 7.5 2 5 6 V mA V mA mW VS = 40 V fOSC = 20 kHz VEXT = 6.2 to 6.7 V Semiconductor Group 7 PSB 2121 Application Informations Undervoltage Lockout The undervoltage lockout circuit protects the PSB 2121 and the power devices from inadequate supply voltage. If VS is too low, the circuit disables this output driver. This ensures that all control functions have been stabilized in the proper state when the turn on voltage (8 V) is reached, and it prevents from the possibility of start up glitches. The undervoltage lockout is programmable by connecting a Z-diode between VS and UV from 8 V up to 70 V. If UV is connected to VS the default undervoltage lockout is 8 V. Voltage Reference The reference regulator of the PSB 2121 is based on a temperature compensated bandgap. This circuitry is fully active at supply voltages above + 6.0 volts and provides up to 0.5 mA of load current to external circuitry at + 4.0 volts. This reference has to be buffered by an external capacitor > 0.5 F. Oscillator The oscillator frequency is programmed by three components: RT, CT and RD as shown in figure 2. The oscillator timing capacitor CT is charged by VREF through RT and discharged by RD. (RD is seriesconnected with an internal 9 k discharge-resistor.) So the rise-time and the fall-time of the sawtooth oscillator can be programmed individually. Figure 2 Semiconductor Group 8 PSB 2121 At the beginning of the discharge period a positive synchronization pulse is generated at pin SYNC. Otherwise the PSB 2121 can be synchronized via pin SYNC to an external logic clock by programming the oscillator to free run at a frequency 10 % lower than the synchronization frequency. The PSB 2121 is synchronized by the rising edge of the sync. signal. So multiple devices can be synchronized together by programming one master unit for the desired frequency. Notice that the frequency of the output driver is half the oscillator frequency. The switching frequency as a function of RT and CT with RD = 0 is shown in figure 3. Figure 3 Switching Frequency Soft Start Circuit The soft start circuit protects the power transistors and rectifier diodes from high current surges during power supply turn-on. When the supply voltage is connected to the PSB 2121 the undervoltage lockout circuit holds the soft start capacitor voltage at zero. When the supply voltage reaches normal operating range an internal 4 A current source will charge the external soft start capacitor. As the soft start voltage ramps up to + 5 volts, the duty cycle of the PWM linearly increases to whatever value the regulation loop requires. Semiconductor Group 9 PSB 2121 Pulse Width Modulator The pulse width modulator compares the sawtooth-voltage of the oscillator output with the input signal at PWMP and with the voltage of the external soft start capacitor at CSS (see figure 1). Error Amplifier Conventional operational amplifier for closed-loop gain and phase compensation. Low output impedance: unity-gain stable Control Logic The control logic inhibits double pulses during one duty cycle and limits the maximum duty cycle to 50 %. Current Limiting A differential input comparator terminates individual output pulses each time when the sensvoltage rises above threshold. When sense voltage rises to 100 mV above threshold a shutdown signal is sent to the control logic. CMOS Supply An integrated 6 V linear voltage regulator supplies the internal low-voltage CMOS-circuits from the input voltage. This supply-voltage is connected to pin VEXT and has to be buffered by an external capacitor (Cmin = 1 F). Power dissipation of the linear voltage regulator can be reduced, if an external supply is used for that purpose by connecting it to pin VEXT. If the input voltage at VEXT reaches 6.2 V the internal linear voltage regulator turns off and the internal CMOS-circuits are fed from the external voltage. In this case the input current at VEXT is approx. 0.5 mA. Note: An internal 7.5 V Z-diode protects the VEXT input against overvoltage. The maximum Z-current is 2 mA! So if the external CMOS-supply isn't stabilized the input current must be limited (e. g. by a resistor). Semiconductor Group 10 PSB 2121 Extended Input Voltage Range Some DC/DC-converter applications require a higher input voltage than the maximum supply voltage of the PSB 2121 which is limited to 70 V. Figure 4 shows a method to extend the input voltage range by connecting a zener-diode between the input voltage and VS of the PSB 2121. Figure 4 If the PSB 2121 is fed via VEXT, the input current at pin VS is approx. 30 A. The additional power losses are accordingly 30 A x VZ; the minimum input voltage is VZ + 8 V. PSB 2121 Applications The PSB 2121 accommodates both galvanically isolated and non-isolated configurations. Figure 5 shows a non-isolated 1 W flyback converter. The converter is fully compatible with the CCITT-power recommendations on the S-interface. At an input voltage of 40 V, the efficiency is 64 % at an input power of 250 mW and 86 % at an input power of 900 mW. Figure 6 shows a 4 W flyback converter with opto isolation to feed the S-bus with 40 V. The maximum input voltage is extended from 70 V to 100 V. Semiconductor Group 11 PSB 2121 Figure 5 Application Circuit Semiconductor Group 12 PSB 2121 Figure 6 Application Circuit Semiconductor Group 13 |
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